Storage of information is crucial to the correct operation of most modern circuits such as digital logic and computer memory. A memory element for storing information receives one or more input signals which can change the value of the stored information, and at least one output for presenting the stored information. The stored information may be a logic value and changing the logic value may comprise changing the stored value between two or more logic states. Two common forms of such memory elements are flip-flops and latches which are examples of bistable multi-vibrators where a logic value held by a circuit can be flipped from one state to another by an external trigger pulse. In common usage, the term flip-flop refers to a synchronous circuit which is edge-sensitive and relies on a clock to ensure its correct operation, and a latch is a circuit which is transparent and is level-sensitive.
FIG. 1 illustrates a prior art latch circuit 100 in which a pair of cross-coupled NOR gates 102, 104 receive respective reset (R) and set (S) signals. The stored bit of information is presented at the output Q with its complement Q also being available as an output if required. The latch of FIG. 1 is transparent, in that an input signal change causes immediate change in its output.
FIG. 2 illustrates a gated version of the latch 100 of FIG. 1. This clocked RS flip-flop 200 includes additional circuitry comprised of a pair of AND gates 202, 204 coupled with an enable signal (E) which may for example be a clock signal, or a read or write strobe signal. The operation of the circuits of FIGS. 1 and 2 is well known to the person skilled in the art and will not be described in detail herein.
A problem that occurs with memory elements is dealing with incoming input signals that overlap. This is illustrated with respect to FIGS. 3a, 3b and 3c which shows the changing of input signals between high and low values (y-axis) over time (x-axis). FIG. 3a shows a normal condition which is expected for ensuring correct operation of an RS flip-flop. Here it can be seen that a set signal pulse (S) rises and falls in a short period of time and there is a large gap before the rise and fall of the reset signal pulse (R). The output Q of the flip-flop is set to a first logic state, “1”, by the rising edge of the set pulse (S) and then reset to a second logic state, “0”, by the rising edge of the reset pulse (R). This operation is stable.
However, in application areas where it is required to change the stored logic value at a high frequency, then it is often the case that the set and reset pulses may overlap and examples of such abnormal conditions are shown in FIG. 3b and FIG. 3c. Both of the abnormal conditions shown in FIGS. 3b and 3c have portions of time (300 and 302 respectively), where both of the set and reset signals are high at the same time. In the case of FIG. 3b the rising edge of the reset pulse occurs during the time when the set pulse is high and in FIG. 3c the rising edge of the set pulse occurs during the time while the reset signal is high.
For the types of latches and flip-flops illustrated in FIGS. 1 and 2, this “1-1” state is forbidden because it breaks the logical equation that the output Q is not its complement. This problem can be solved by adding gates to the inputs that converts the 1-1 state to one of the non-restricted combinations, resulting in either an S-dominated latch or an R-dominated latch or by toggling the output as seen in a JK latch.
However, even with these solutions, there are still fundamental problems in high frequency applications in dealing with the overlap of set or reset functions. Therefore, an improved memory element that provides better characteristics is desired.